276 to 300 of 466 SystemVerilog Jobs in the UK

ASIC Design Engineer Edinburgh Global Semiconductor leader As an ASIC Design engineer, you will get the opportunity to work in the beautiful City of Edinburgh. Working in the heart of Edinburgh means being surrounded by stunning architecture, rich history, and More ❯

Social network you want to login/join with: col-narrow-left Client: Enterprise Recruitment Ltd Location: portsmouth, hampshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 16.06.2025 Expiry Date: 31.07.2025 More ❯

Swedium Global Services is a growing System Engineering and Solution Company, offering services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy, and Outsourcing services to our clients More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

Senior FPGA Engineer | £80-100k | Slough | Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

They're looking for a Staff Verification Engineer. Principal Verification Engineer Responsibilities: Develop and execute verification plans in collaboration with design and systems teams. Create and maintain testbenches using SystemVerilog, UVM. Work closely with RTL designers to understand architectural intent and corner cases. Write and review functional coverage models to ensure complete design verification. Requirements: Extensive experience with SystemVerilog and More ❯

analysis. Provide verification reports to demonstrate all tests passing on the RTL. Utilize methodologies including design checks, verification techniques with simulators and emulators such as UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years’ experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs … Requirements: 5+ years’ experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these More ❯

be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years’ experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs … Requirements: 5+ years’ experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these More ❯

be, please get in touch. 1. Verification Lead (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Leadership role managing SoC/IP-level verification Requirements: 6+ years experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Type: Contract (Outside IR35) Focus: RISC-V, GPU, AI, complex SoCs … Requirements: 5+ years experience, SystemVerilog/UVM, scripting 3. Junior/Mid-Level Verification Engineer (Permanent) Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these More ❯

on analysis of coverage gaps. Provide verification reports showing all tests passing on the RTL. Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

on coverage gap analysis. Provide verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

of coverage gaps. Provide verification reports showing all implemented tests passing on the RTL. Utilize methodologies including design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

analysis of coverage gaps. Provide verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

based on analysis of coverage gaps. Provide verification reports demonstrating all tests passing on RTL. Utilize methodologies including design checks, verification with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

analysis of coverage gaps Provide verification reports showing all tests passing on the RTL Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog-based testbenches, and C, SystemVerilog, UVM-based test cases #J-18808-Ljbffr More ❯

coverage gaps Provide verification reports to show all implemented tests passing on the RTL Methodologies will include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based testcases #J-18808-Ljbffr More ❯

are looking for real impact and innovation, or know someone who might be, please get in touch. Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Requirements: 6+ years’ experience, strong SystemVerilog/UVM, team mentorship 2. Hardware Verification Engineer (Permanent/Contract) Location: Hemel Hempstead, UK (Hybrid Preferred | Remote Considered) Focus: RISC-V, GPU, AI, complex SoCs Requirements: 5+ years’ experience … SystemVerilog/UVM, scripting Location: Hertfordshire, UK (Hybrid/Onsite Flexible) Perfect for engineers early in their verification careers Requirements: 1+ year experience, familiarity with SystemVerilog/UVM If any of these sound like a fit, please feel free to reach out or send your CV. If these roles are not for you, please do pass them along to anyone More ❯

on analysis of coverage gaps. • Provide verification reports to demonstrate all tests passing on RTL. • Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

as needed to show all implemented tests passing on the RTL. Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based testcases. #J-18808-Ljbffr More ❯

next-generation chip architectures in areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend RTL Design + Strong Experience … with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience – pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus scheme, and a strong benefits package. If you are a driven and experienced IC Design More ❯

next-generation chip architectures in areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend RTL Design + Strong Experience … with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience – pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus scheme, and a strong benefits package. If you are a driven and experienced IC Design More ❯