101 to 125 of 257 SystemVerilog Jobs

compliance. Support test and lab evaluation using signal generators, spectrum analysers, and oscilloscopes. Lead or contribute to the implementation of designs using VHDL, SystemVerilog, and MATLAB/Simulink HDL Coder. Develop low-level C software for FPGA bring-up, test, and integration. Use industry-standard tools such as Vivado, Quartus … consultation across teams. Essential Experience Proven track record in delivering FPGA designs for real-time, high-speed, or RF-centric systems. Proficiency in VHDL, SystemVerilog, and embedded C for FPGA-host integration, control, and testing. Experience with MATLAB/Simulink and HDL Coder for algorithm-to-hardware workflows. Proven ability ...

## VHDL FPGA Firmware EngineerApplylocations: GB - Southampton: GB - Bristol - Coldharbour Lanetime type: Full timeposted on: Posted Todayjob requisition id: R0026952**Job Description:****Salary Ranges**Engineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary ...

Are you an experienced FPGA Designer who enjoys contributing to the development of complex FPGA platforms? Look no further! Join our ambitious team at MBDA and be part of a company that is at the ...

Job Description:Salary RangesEngineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

Job Description:Salary RangesEngineer: £38k - £53kSenior: £45k - £61kLeonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range ...

critical IP, collaborating with graphics architecture, verification and physical design teams. The role covers design flow from concept to physical handoff and requires SystemVerilog/VHDL experience; preferred knowledge in architecture and scripting languages. Apple emphasises inclusion and accessibility. #J-18808-Ljbffr ...

Bristol, UK is seeking a Senior Verification Engineer to lead RTL verification across ASIC/FPGA platforms. You will develop verification plans, build SystemVerilog/UVM environments and drive coverage-driven verification for complex wireless IP and modem subsystems. You will collaborate across multiple teams, mentor junior engineers, and contribute ...

under senior guidance to support real-world trading applications. You will work closely with software engineers, quantitative traders, and researchers, applying your knowledge of SystemVerilog or Verilog and languages like C++ or Python to advance trading technology. #J-18808-Ljbffr ...

collaborating with architecture, verification, software, and implementation teams to deliver high-quality silicon solutions. The role requires strong RTL/verification experience, RTL languages (SystemVerilog/Verilog/VHDL), EDA tools, and proficiency in scripting. #J-18808-Ljbffr ...

advanced verification techniques including functional coverage and assertions. Strong scripting skills are beneficial for automation. Candidate should have expertise in Verilog/SystemVerilog, UVM/OVM methodologies, and experience with IC design verification from tape-out to closure. #J-18808-Ljbffr ...

features, timing, area and power goals. Responsibilities include RTL design, clocking, CDC/RDC verification, and mentoring junior engineers. The role requires expertise in SystemVerilog/VHDL and proficiency with revision control systems, with #J-18808-Ljbffr ...

test scenarios and assertions, and collaborate with Analog and Digital Design engineers across the AMS DV team. The role focuses on self-checking verification, SystemVerilog UVM, and power/timing analyses, with opportunities to advance verification techniques and toolchains in a cutting-edge environment. #J-18808-Ljbffr ...

digital development, architecture, RTL design, verification and supporting silicon bring-up. You will own digital control interfaces, clocks and calibration with Verilog/SystemVerilog, build verification environments and collaborate closely with analogue engineers for tight integration of mixed-signal blocks. #J-18808-Ljbffr ...

constrained random tests to verify complex designs. You’ll develop coverage points, analyze results, and refine verification environments to reach full coverage. Strong SystemVerilog/UVM knowledge and scripting abilities are essential. #J-18808-Ljbffr ...

engineers, improve design processes and collaborate with algorithm, system architecture and software teams. Experience leading FPGA/digital design teams, RTL in Verilog/SystemVerilog, and delivering complex IP across #J-18808-Ljbffr ...

open-source silicon used in production devices. What they're looking for: 3 5 years' industry experience in Digital Design Verification. Strong hands-on SystemVerilog and UVM experience. Experience developing and debugging UVM testbenches. Some exposure to Formal Verification . Understanding of verification planning, functional coverage and regression testing. Python ...

advanced, open-source silicon used in production devices. What they're looking for: 35 years' industry experience in Digital Design Verification. Strong hands-on SystemVerilog and UVM experience. Experience developing and debugging UVM testbenches. Some exposure to Formal Verification . Understanding of verification planning, functional coverage and regression testing. Python ...

open-source silicon used in production devices. What they're looking for: 3–5 years' industry experience in Digital Design Verification. Strong hands-on SystemVerilog and UVM experience. Experience developing and debugging UVM testbenches. Some exposure to Formal Verification . Understanding of verification planning, functional coverage and regression testing. Python ...

open-source silicon used in production devices. What they're looking for: 3–5 years' industry experience in Digital Design Verification. Strong hands-on SystemVerilog and UVM experience. Experience developing and debugging UVM testbenches. Some exposure to Formal Verification . Understanding of verification planning, functional coverage and regression testing. Python ...

Senior Digital ASIC Design Engineer will have: Strong commercial experience in ASIC, SoC or digital IC design Solid hands on experience with Verilog or SystemVerilog RTL Strong understanding of the digital design flow from RTL through synthesis and implementation Experience taking complex designs through development and integration Good understanding ...

open-source silicon used in production devices. What they're looking for: 3–5 years' industry experience in Digital Design Verification. Strong hands-on SystemVerilog and UVM experience. Experience developing and debugging UVM testbenches. Some exposure to Formal Verification . Understanding of verification planning, functional coverage and regression testing. Python ...

successful in this role you will also need experience of toolchains such as Vivado or Quartus and a HDL language such as VHDL or SystemVerilog, and experience in running simulations and testbenches and performing hardware-level debugging. The company are offering tailored packages for the right engineer, which includes ...

improve development efficiency through new tools, methodologies and emerging technologies Required experience: Strong commercial experience in RTL design using Verilog and/or SystemVerilog Previous line management or people management experience within an engineering environment Experience leading technical projects and coordinating engineers towards successful delivery Experience working with industry standard ...

netlist and layout issues Strong written communication for documenting root causes and fixes Nice to have Photonic IC verification experience Experience with Verilog/SystemVerilog netlists Exposure to foundry PDK qualification Experience building internal automation to scale verification #J-18808-Ljbffr ...

/or low area and understanding of how RTL will map to gate-level structuresFamiliarity with the frontend design flowExperience with hardware description languages - SystemVerilog would be desirableFluency in English (mandatory)Please send us your CV in English.#WeAreIn for driving decarbonization and digitalization.As a global leader in semiconductor solutions ...