26 to 35 of 35 SystemVerilog Jobs

exciting opportunity for a Senior Staff Verification Engineer to join a global R&D organisation. In this role, you will be responsible for developing SystemVerilog UVM testbench environments for IP-level verification, as well as designing and implementing new UVM verification components. You will ensure that verification environments meet … verification strategy and testbench architecture across the business. Key Requirements Minimum of 7 years’ experience in hardware verification, ideally at IP level, using SystemVerilog and UVM Advanced expertise in UVM, SystemVerilog, and SystemVerilog Assertions (SVAs) Experience developing verification platforms and frameworks Proven ownership of IP verification, including delivery against defined ...

delivering first-time success with complex mixed-signal ICs Metric-driven verification: planning, requirements extraction, directed & constrained-random verification, functional and code coverage analysis SystemVerilog, including SVA (SystemVerilog Assertions) Testbench design using verification frameworks such as UVM, OVM, e, or VMM Strong RTL/testbench debugging skills (including gate-level ...

Job Title: Microarchitect & RTL Design Engineer Location: England, United Kingdom (office location yet to be determined) About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture ...

more balanced and rewarding lifestyle. Key Responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain testbenches using SystemVerilog and UVM Write and debug test cases to validate functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … practices Manage and debug gate-level simulations Qualifications 10+ years of experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and industry-standard simulation tools Solid understanding of digital design fundamentals, RTL design, and ASIC development flows Experience with scripting languages such as Python ...

NoC Architect Baya Systems , Greater Cambridge, UK -or- elsewhere in the UK hybrid/remote Job Title: NoC Architect About the role: We are seeking a NoC Architect with prior research experience in Networks-on ...

A Senior Mixed Signal Verification Engineer will join an exciting Semiconductor Scale-up to undertake digital, mixed signal and analog verification related to high speed Serdes designs. You’ll bring 10+ years’ Verification experience, strong ...

Take the initiative in developing reusable RTL for implementing clever algorithms For this role, we are seeking an academically bright candidate, PhD-qualified in a numerate stem subject such as physics, maths, electronics, or electronics ...

What you’ll do Work closely with hardware designers and system architects to define and own verification plans based on design specifications Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models Design and run self-checking, directed, and randomized tests Maintain the verification environment, including tracking regressions, bugs … commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already ...

designs using advanced verification methodologies. Key responsibilities Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog testbenches. Write, debug, and execute test cases to verify functionality, performance, and corner cases Perform block-level and full-chip verification, including simulation, coverage analysis … continuous improvement of design and verification best practices Qualifications 5+ years’ experience in digital and/or mixed-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting ...

passion for building cutting-edge silicon. Responsibilities Collaborates with cross-functional teams to define and implement ASIC architectures Designs and develops RTL code using SystemVerilog and Verilog Conducts design verification and ensures compliance with specifications Participates in the integration and testing of ASICs Contributes to the improvement of design methodologies … Bachelor's or Master's degree in Electrical Engineering or related field Demonstrates a solid understanding of ASIC design principles and methodologies Proficient in SystemVerilog, Verilog, and RTL Design Possesses familiarity with security-related applications and protocols, which is a plus Exhibits strong problem-solving skills and attention to detail ...