Cambridge, England, United Kingdom Hybrid / WFH Options
Platform Recruitment
new silicon chips. Qualifications and Experience: Strong experience in analogue custom IC design. Strong experience with modelling and verification for ASIC implementation. Experience with SystemVerilog and Verilog-A. EDA tool experience for custom analogue IC development like Cadence, Mentor Graphics. more »
s degree in Electrical/Electronic Engineering or related field. 2 - 10 years of experience in RTL design and verification for FPGAs using Verilog, SystemVerilog, or VHDL. Experience with Vivado/Quartus A Software Engineering and Hardware Engineering background is a plus Desirable Skills: Knowledge of networking protocols, such as more »
of cutting edge, high-performance computing processors! We are particularly looking for engineers with experience in: Verification and/or design of complex SoC SystemVerilog/UVM/VHDL SystemC/C++ Embedded C scripting languages like Bash/Perl/Python Experience in the following are a plus: Experience more »
Implementing Regression tests Performing Formal Verification Working closely with IC designers and post-silicon engineers Qualifications and Background Requirements: Knowledge/experience with HDL (SystemVerilog/Verilog/VHDL), particularly for testbenches creation Knowledge/experience in scripting languages, such as Tcl and Python Some knowledge of ASIC design flow more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus. You will be part of a company where the work environment is stimulating and exciting, as you more »
/Physics etc. Processor architecture, ARM, CPU, RISC-V etc SOC design and architecture, IP integration Confident ability in RTL design (Verilog/VHDL , SystemVerilog) for ASIC/FPGA Proven ability in tape-out and IP development and delivery processes Bonus/"nice-to-have" skills: High Speed Communication, Protocols more »
Science or similar A number of years’ experience working on the verification phase for digital ASICs Hands on experience in VHDL/Verilog/SystemVerilog Code/script development experience using assembler, perl, C/C++. An ability to learn quickly and work unsupervised or as part of a team more »
Electronic Engineering or similar A proven background working as a Digital IC Design Engineer, with solid hands-on skills in RTL design - Verilog/SystemVerilog (circa 5-10+ years' experience), and digital-analog integration A good handle on ASIC Verification activities Physical implementation knowledge Excellent communication skills in English more »
team members, in collaboration with our international team(s) The ideal candidates for this position will have: Delivered with (as applicable) SoC design verification, SystemVerilog languages (UVM, SVA, SFC), low power verification (UPF methodology), software/hardware co-verification (SystemC/C/C++), Interfaced with designs/teams with more »
to enhancing Verification strategy and architecture of IP testbenches.Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
to enhancing Verification strategy and architecture of IP testbenches.Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
Knowledge of RTL design. Knowledge of the full design flow (including some middle end knowledge - STA, Synthesis, etc.) Proficient in a programming language (Verilog, SystemVerilog, etc.) Scripting knowledge (Python or C/C++) Experience leading projects or mentoring junior engineers. If you are interested in finding out more, or applying more »
Knowledge of RTL design. Knowledge of the full design flow (including some middle end knowledge - STA, Synthesis, etc.) Proficient in a programming language (Verilog, SystemVerilog, etc.) Scripting knowledge (Python or C/C++) Experience leading projects or mentoring junior engineers. If you are interested in finding out more, or applying more »
years of experience in ASIC development Expertise in verification methodologies & tools Strong knowledge of UVM Excellent programming skills in hardware description languages (e.g. SystemVerilog) Good programming skills in scripting languages (e.g. Python, Perl, Tcl) Excellent written and verbal communication skills in English For more information and to apply, please contact more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus.You will be part of a company where the work environment is stimulating and exciting, as you are more »
Full and deep understanding of the CPU architectures is an advantage; Expertise in hardware verification languages such as SV UVM, UVM and SVAs, and SystemVerilog; Knowledge of verification platform and framework development, RTL and Gate level (optional) functional verification; Proven experience of IP/Sub-System/SoC verification including more »
full chip and block level logic verification. Experience developing complex UVM verification environments. Technical leadership experience. Experience developing test benches from scratch. Knowledge of SystemVerilog and Verilog. Experience mentoring junior Engineers. If you are interested in finding out more, or applying for this position, please contact Lucy Edmondson more »
and coordination skills, with a successful track record of building and managing engineering teams In-depth understanding of RTL languages (VHDL/Verilog/SystemVerilog/SystemC/Python) A good understanding of software engineering and architectural principles Strong language skills in both English and FrenchAn excellent salary is on more »
gadgets on the market today and in the future. The ideal candidate will have: Proven experience of digital ASIC verification techniques Strong experience in SystemVerilog or Verilog testbench creation Experience with OVM, VMM, UVM methodologies Effective problem solving, communication and team working skills (essential!) This position offers the opportunity to more »
am looking for someone with some of the following experience: System-level modelling and simulation of analog and mixed-signal circuits. Basic understanding of SystemVerilog and assertions (preferred). Proficiency in scripting languages (Perl or Python). In-depth knowledge of circuit analysis, optimisation, stress, and reliability analysis. Familiarity with more »
years of experience in silicon verification, with a strong focus on processor verification especially using instruction set simulators is desired. Verification Expertise: Proficiency in SystemVerilog and C/C++ or Python for designing and implementing testbenches, and test cases for processor verification. You must already be based in Europe to more »
A Bachelors or Masters degree in Electronic Engineering or related field A strong background within RTL Design and Verification with VHDL/Verilog/SystemVerilog An understanding of processor architecture is desirableOur client offers a competitive pay package, a very positive ‘work-life’ balance and a great place to learn more »
tools. eg. Cadence, Jasper Gold, Siemens EDA QuestaFormal, or Synopsys. Keywords: Formal Verification/Semiconductor/Semi conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification more »
Microprocessor architecture (CPU) and have at least 6 years’ experience in processor verification. Experience in unit and full chip level test benches. Fluent in Systemverilog, C/C++ and Python. Knowledge of RISC-V ISA would be advantageous. Your benefits package will depend on position, but your benefits programme will more »
