TITLE: ASIC FPGA Engineer with ACTIVE Secret clearance (US Citizenship REQUIRED) RATE RANGE: $55/hr W2 - $65/hr W2 (no health benefits while on contract) CLEARANCE: Active Secret Security Clearance required LOCATION: Onsite in Bloomington MN 55431 (no More ❯
A Senior ASIC/FPGA Hardware Engineer for Cryptographic Systems architects, specifies, and ensures proper design & implementation of hardware-based security solutions. The engineer develops the architecture and specification for ASIC or FPGA-based hardware designs. They translate those requirements More ❯
Title: FPGA Verification Engineer Location: Arlington VA, or Annapolis Junction, MD or Denver, CO Security Clearance: TS/SCI required Job Type: Full-Time; 100% On site Position Overview ClearanceJobs' customer is seeking a highly skilled FPGA Verification Engineer to More ❯
Check out this new opportunity! Sr ASIC/FPGA Electrical Engineer Canonsburg, PA Contract Position Pay Estimated: $72.24-$84.50/Hour This estimate represents the typical salary range for this position based on experience and other factors, (geographical location, etc. More ❯
Job Description: •Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. •Determines architecture design, logic design, and system simulation. •Assignments include the analysis of all aspects from high-level design to synthesis More ❯
Manchester, Lancashire, United Kingdom Hybrid / WFH Options
Arm Limited
data analysis. "Nice To Have" Skills and Experience : Experience with SoC-level performance analysis and tools. Familiarity with memory subsystem micro-architecture and performance implications. Experience with Verilog/SystemVerilog RTL, including analysis and debugging in collaboration with design teams. Working knowledge of AMBA protocols and transaction-level modeling (SystemC/TLM). Exposure to Verilog/SystemVerilog and interaction More ❯
We are seeking talented and motivated individuals to tackle challenging engineering problems in advanced digital IC design. As a Senior Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies. You will be responsible More ❯
Our DoD/Aerospace client is looking to fill an Advanced ASIC FPGA Engineer position that just opened in Bloomington, MN. In this role, you be responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and More ❯
Position Overview LCS Defense is seeking a highly skilled FPGA Verification Engineer to join our classified hardware development team. The ideal candidate will develop and implement comprehensive verification strategies, including formal methods, for complex FPGA designs in high-assurance applications. More ❯
and space-qualified ASICs. As an FPGA Engineer, you will: Translate complex signal processing algorithms into efficient RTL architectures Design and verify FPGA and ASIC IP using Verilog/SystemVerilog Validate and integrate designs on the latest FPGA development platforms Collaborate across architecture, verification, and physical implementation teams Contribute to UVM test environments and technical documentation Key skills required for … the FPGA Engineer: Strong RTL experience (Verilog/SystemVerilog) targeting FPGAs or ASICs Skilled in timing closure, synthesis, and power/resource optimisation Experience working on high-throughput digital signal processing blocks Familiarity with communications algorithms (e.g. FEC, beamforming) is a bonus Knowledge of UVM, scripting (Python), or AMBA protocols is desirable If you’re interested in the position of More ❯
D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. … in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such More ❯
D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable test benches Work with design teams test plans, failure debug, coverage, etc. … in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such More ❯
Advanced FPGA Engineer Location: Bloomington, MN Responsibilities: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of More ❯
Title Hardware Engineer Location Annapolis Junction Description This position is contingent upon contract award Markesman Group is seeking Hardware Engineers to join our team at Annapolis Junction, Maryland. Candidates for this position will contribute to the team by utilizing in More ❯
Microarchitect & RTL Design Engineer Cambridge,/Bristol England, United Kingdom We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified More ❯
Microarchitect & RTL Design Engineer Cambridge,/Bristol England, United Kingdom We are a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified More ❯
growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯
growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯
growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯
growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off … verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA tools and scripting languages. More ❯
