351 to 375 of 433 SystemVerilog Jobs

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is More ❯

Join to apply for the Principal Verification Engineer (f/m/div) role at Infineon Technologies 2 weeks ago Be among the first 25 applicants Join to apply for the Principal Verification Engineer (f/m/div) role More ❯

Job Title: Microarchitect & RTL Design Engineer Location: Santa Clara, CA About the Role: We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role More ❯

Swedium Global Services is a growing System Engineering and Solution Company, offering services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy, and Outsourcing services to our clients More ❯

verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;Strong background in PSS/UVM/SystemVerilog; Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;Strong analytical skills and attention to More ❯

verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

APB, and at least one variant of AXI, including AXI3, AXI4, AXI4-Lite, ACE, or AXI5 Proficient RTL design skills using VHDL, Verilog, or SystemVerilog Solid understanding of functional verification, ideally using SystemVerilog Demonstrated leadership in complex IP and full ASIC design projects from concept through to RTL completion. Knowledge More ❯

APB, and at least one variant of AXI, including AXI3, AXI4, AXI4-Lite, ACE, or AXI5 Proficient RTL design skills using VHDL, Verilog, or SystemVerilog Solid understanding of functional verification, ideally using SystemVerilog Demonstrated leadership in complex IP and full ASIC design projects from concept through to RTL completion. Knowledge More ❯

Design Engineer is sought to join a dynamic team. The ideal candidate will have a strong background in RTL Design and be proficient in SystemVerilog and Verilog. This position offers the opportunity to work on cutting-edge projects and contribute to the development of innovative solutions in the field of … working with and huge growth plans. Responsibilities Collaborates with cross-functional teams to define and implement ASIC architectures Designs and develops RTL code using SystemVerilog and Verilog Conducts design verification and ensures compliance with specifications Participates in the integration and testing of ASICs Contributes to the improvement of design methodologies … Bachelor's or Master's degree in Electrical Engineering or related field Demonstrates a solid understanding of ASIC design principles and methodologies Proficient in SystemVerilog, Verilog, and RTL Design Possesses familiarity with security-related applications and protocols, which is a plus Exhibits strong problem-solving skills and attention to detail More ❯

experienced ASIC Design Engineer is sought to join a dynamic team. You will have a strong background in RTL Design and be proficient in SystemVerilog and Verilog. This position offers the opportunity to work on cutting-edge projects and contribute to the development of innovative solutions in the field of … of clients and ambitious growth plans. Responsibilities Collaborate with cross-functional teams to define and implement ASIC architectures Design and develop RTL code using SystemVerilog and Verilog Conduct design verification and ensure compliance with specifications Participate in the integration and testing of ASICs Contribute to improving design methodologies and processes … Qualifications Bachelor's or Master's degree in Electrical Engineering or related field Solid understanding of ASIC design principles and methodologies Proficiency in SystemVerilog, Verilog, and RTL Design Familiarity with security-related applications and protocols (a plus) Strong problem-solving skills and attention to detail Daily Responsibilities Collaborate with engineers More ❯

areas like memory, interconnect, and high-speed interface design. Key Responsibilities: + Develop and Integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) + Undertake Digital IC Design processes & Perform design synthesis, linting + Complete projects from conception to completion Skills Required: + Experience with frontend … RTL Design + Strong Experience with SystemVerilog, Verilog or VHDL + Has had exposure to ASIC design flow (Lint, syntheisis, simulation) + Digital Design Principles experience pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit into the office every month. A competitive salary, bonus More ❯

experience with formal verification tools (e.g., Cadence JasperGold, Synopsys VC Formal, or equivalent tools). Hands-on experience with RTL design such as Verilog, SystemVerilog, or VHDL. Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience with assertions (e.g., SVA - SystemVerilog Assertions More ❯

technical decision-making Document technical specifications and development progress Contribute to bring-up, synthesis, and physical-aware design flows Verification Responsibilities: Develop UVM/SystemVerilog testbenches and functional verification plans Implement directed and constrained-random tests for robust coverage Execute regression testing, debug RTL, and track issues to resolution Verify … Measure and validate system performance and functional correctness Collaborate closely with RTL designers and architects Design Requirements: 5+ years of experience in RTL design (SystemVerilog or VHDL) Deep knowledge of digital design principles and computer architecture Experience with GPU, vector processors, or AI accelerator design Familiarity with RISC-V instruction … Electrical Engineering, Computer Engineering, or related field Verification Requirements: 5+ years of experience in hardware verification (complex SoCs preferred) Strong understanding of UVM and SystemVerilog methodologies Experience with advanced verification techniques (coverage, assertions, formal) Familiarity with RISC-V and GPU/AI architectures (preferred) Proficient with simulators and debug tools More ❯

a 6-month fixed contract with a view to go into a permanent position. The Lead Verification Engineer will have expertise in UVM and SystemVerilog to support the development and verification of complex ASIC designs. Responsibilities Develop and implement verification environments using UVM methodology Create verification plans and test cases … methodology improvements and best practices Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science 10+ years industry experience Proficiency in SystemVerilog and UVM for ASIC verification Solid understanding of digital design fundamentals Experience with industry-standard simulation and verification tools Strong problem-solving skills and attention More ❯

Senior Verification Engineer - Ghent I am seeking a highly experienced Senior Verification Engineer to join a leading organisation at the forefront of semiconductor innovation. This is an exceptional opportunity to be part of a dynamic and multicultural team, working on More ❯

Social network you want to login/join with: col-narrow-left Client: Enterprise Recruitment Ltd Location: portsmouth, hampshire, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 4 Posted: 16.06.2025 Expiry Date: 31.07.2025 More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

ASIC Design Engineer Edinburgh Global Semiconductor leader As an ASIC Design engineer, you will get the opportunity to work in the beautiful City of Edinburgh. Working in the heart of Edinburgh means being surrounded by stunning architecture, rich history, and More ❯

Senior FPGA Engineer £80-100k Slough Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

Senior FPGA Engineer | £80-100k | Slough | Hybrid My client's innovative technologies have facilitated the deployment of high-speed internet and robust communication networks for remote and underserved areas, fostering digital inclusion and supporting the growth of smart cities More ❯

demonstrate all tests passing on the RTL. Utilize methodologies including design checks, verification techniques with simulators and emulators such as UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

gaps. Provide verification reports demonstrating all tests passing on RTL. Utilize methodologies including design checks, verification with simulators and emulators: UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

Provide verification reports showing all tests passing on the RTL. Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM test cases. #J-18808-Ljbffr More ❯

verification reports showing all tests passing on the RTL. Use methodologies including design checks, verification techniques with simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯

reports showing all implemented tests passing on the RTL. Utilize methodologies including design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases. #J-18808-Ljbffr More ❯