101 to 125 of 182 SystemVerilog Jobs

will translate high-level requirements into robust digital designs and verification environments. Collaborate with design and architecture teams to identify bugs, develop testbenches with SystemVerilog/UVM, drive coverage closure, mentor junior engineers, and document specs and verification reports. #J-18808-Ljbffr ...

Graphics Design Verification Engineer to contribute to pre-silicon RTL verification for high-performance graphics IP in mobile devices and PCs. You will use SystemVerilog, UVM, C++, and scripting to build test benches, generate tests, run simulations, and drive complex IPs to high-quality closure. Collaboration with Architecture, Design ...

Graphics group. Key responsibilities include developing testbenches with sequences, checkers, and coverage plans, troubleshooting and debugging, and reporting verification metrics to stakeholders. Strong SystemVerilog/UVM skills and scripting ability are essential. #J-18808-Ljbffr ...

compute teams in Cambridge and Bristol. You will verify complex ASIC/processor designs, develop verification plans, and drive coverage to closure using SystemVerilog, UVM, SVA, and Python. Join a team at the forefront of AI compute and processor technology with flexible working and a strong compensation package ...

will develop RTL, SDC/UPF constraints, integrate IPs and work with verification and implementation teams to ensure high‐quality designs. The role requires SystemVerilog/Verilog HDL skills, strong RTL design grounding, UNIX scripting, and collaboration across CPU, GPU, multimedia IP. #J-18808-Ljbffr ...

complex IPs such as Crypto Accelerators, HW DVFS components, PCIe controllers, and interconnect fabrics, ensuring integration with software. You will write test plans, develop SystemVerilog testbenches and C-based tests, debug failures and collaborate across multiple engineering teams to enable robust, high-quality silicon solutions. #J-18808-Ljbffr ...

teams to improve netlist quality milestones and push forward advanced GPU products. The role requires a BSc in EE and experience with Verilog or SystemVerilog and scripting; knowledge of physical synthesis, timing analysis, and DFT is preferred. Apple values inclusive hiring and accessibility. #J-18808-Ljbffr ...

Technologies International Ltd in Cambridge seeks an ASIC verification specialist with hands-on FPV experience to advance GPU RTL verification pipelines. You will write SystemVerilog assertions, develop formal testbenches, and collaborate with global teams to achieve formal sign-off using JasperGold and related tools. Qualifications include a Bachelor’s degree ...

ASIC Verification Engineer specializing in Formal Property Verification (FPV) to join the Engineering Group > ASICS Engineering. You will develop FPV test plans, write SystemVerilog Assertions, and collaborate with global RTL design and DV teams to drive sign-off. The role requires 2+ years in ASIC design/verification, a degree ...

London. The role involves delivering emulation capabilities for GPU designs while collaborating with design and software teams. Candidates should have strong knowledge in SystemVerilog, debugging skills, and proficiency in programming languages such as Python, C, and C++. The position offers the opportunity to innovate and be part of a dynamic ...

complex, large-scale GPU projects. This role involves micro-architecture development, logic synthesis, and debugging of design issues. Ideal candidates will have experience with SystemVerilog, VHDL, and strong problem-solving skills. The team values diverse perspectives, promoting an inclusive work environment. Join us to influence the design flow of cutting ...

level assembly, and collaborate with graphics architecture, verification, and physical design teams to meet performance and power goals. The role requires deep SystemVerilog/VHDL expertise, strong problem-solving skills, and experience with large-scale SoC or GPU design. #J-18808-Ljbffr ...

seeking penultimate or final-year students or graduates to join the FPGA team. You will design and optimise ultra-low-latency FPGA pipelines, using SystemVerilog and high-performance languages to ship real market-facing code. We value curiosity, practical software and hardware work, and the ability to work across hardware ...

Kelvin operation in a cutting-edge quantum computing ecosystem. The role demands 5+ years in digital/mixed-signal IC design, strong Verilog/SystemVerilog skills, and experience with CTS/STA, DFT, and physical design flows. #J-18808-Ljbffr ...

will develop UVM testbenches, lead verification activities, and ensure project closure through metrics tracking. The ideal candidate will demonstrate strong expertise in verification methodologies, SystemVerilog, and communication skills to collaborate effectively across teams. By joining us, you will contribute to cutting-edge graphics technology utilized worldwide. Embrace the opportunity ...

role entails constructing verification environments, collaborating closely with design engineers, and ensuring high-quality, bug-free designs. Candidates should have a strong background in SystemVerilog and UVM, along with proficiency in Object Oriented Programming. This position offers the chance to work on cutting-edge technologies that impact millions of customers ...

Debug and analyse top-level design issues Codeline management, supporting multiple products & chips Review RTL implementations and mentor junior engineers Minimum Qualifications Expertise in SystemVerilog/VHDL and proficiency in revision control systems Strong problem-solving skills, ability to work across team boundaries and be productive under aggressive schedules Preferred ...

with design, verification and software driver teams Required Skills and Experience Experience in hardware verification methodology and planning Programming skills including Hardware Description Languages (SystemVerilog/UVM) Proficiency in problem solving and debugging Nice To Have Skills and Experience Experience with reusing and integrating external VIPs Experience in Python ...

determine implementation approaches, and design testbenches. Expertise in root‐cause analysis of complex issues, with the ability to resolve them efficiently. Deep knowledge of SystemVerilog and UVM. Capability to develop and enhance verification flows. Familiarity with ASIC design methodologies, flows, and tools. Proficiency in planning, estimating, and tracking personal tasks. ...

incident response workflows for Fractile's infrastructure. IaC TODO Scale and maintain Fractile's Bazel monorepo as we continue growing across Python, C++, Rust, SystemVerilog, and ML workloads. Shape the infrastructure and platform experience for every engineer at Fractile. About You You bring deep infrastructure and build systems expertise alongside ...

stack is, in fact, in Java). However, once you are here, you will be exposed to a diverse tech stack including Python, TypeScript, SystemVerilog (for FPGAs), Raft, Kubernetes, DLT, Angular, and more. The Package Equity: We offer real equity options. You are building the company’s value ...

Job Description: Salary: Engineer: £37,400 to £53,550/Senior: £45, 200 to £61,950/Principal: £53,300 to £71,400/Lead: £59,400 to £84,955 Leonardo UK operates a grade ...

Are you ready to shape the future of cutting-edge technology? Leonardo, a global leader in advanced electronics, is seeking Firmware/FPGA Engineers at various levels to join our innovative teams across the UK. ...

Join us at Entrust. From our comprehensive portfolio of solutions to our flexible, global workplace, we empower careers, foster collaboration, and build solutions that help keep the world moving safely. Position Overview Provides technical leadership ...

Job Title: FPGA Engineer Location: Basildon, Essex - Hybrid 3+ days on-site per week Role Type : Permanent Salary: £55,000 - £80,000 depending on experience Our client, an established engineering consultancy, require an experienced FPGA ...