251 to 257 of 257 SystemVerilog Jobs

Selection changes the language of the page/content Front-End Implementation (Synthesis) Engineer Imagine working in a team where the only limits are the laws of physics and your imagination.At Apple, phenomenal ideas have ...

Selection changes the language of the page/content Imagine working in a team where the only limits are the laws of physics and your imagination.At Apple, phenomenal ideas have a way of becoming phenomenal ...

signal verification experience on complex SoCs or mixed-signal IP. Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real/wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator). Proficiency in SystemVerilog, with solid assertion ...

wider engineering teams across Europe. Responsibilities will include: Providing technical leadership across ASIC/SoC Digital Verification. Driving verification strategy, planning and execution. Leading SystemVerilog and UVM testbench development. Overseeing functional coverage, debug and verification closure. Mentoring and supporting Senior and Verification Engineers. Collaborating with RTL design, architecture and engineering … Verification Engineers. Technical leaders with the ability to build and develop a high-performing verification team. Technical Background ASIC/SoC Digital Verification. Strong SystemVerilog and UVM. Functional Verification and Coverage Closure. Formal Verification. RISC-V processor and SoC verification. Experience leading verification projects or mentoring DV engineers. Why Consider ...

wider engineering teams across Europe. Responsibilities will include: Providing technical leadership across ASIC/SoC Digital Verification. Driving verification strategy, planning and execution. Leading SystemVerilog and UVM testbench development. Overseeing functional coverage, debug and verification closure. Mentoring and supporting Senior and Verification Engineers. Collaborating with RTL design, architecture and engineering … Verification Engineers. Technical leaders with the ability to build and develop a high-performing verification team. Technical Background ASIC/SoC Digital Verification. Strong SystemVerilog and UVM. Functional Verification and Coverage Closure. Formal Verification. RISC-V processor and SoC verification. Experience leading verification projects or mentoring DV engineers. Why Consider ...

wider engineering teams across Europe. Responsibilities will include: Providing technical leadership across ASIC/SoC Digital Verification. Driving verification strategy, planning and execution. Leading SystemVerilog and UVM testbench development. Overseeing functional coverage, debug and verification closure. Mentoring and supporting Senior and Verification Engineers. Collaborating with RTL design, architecture and engineering … Verification Engineers. Technical leaders with the ability to build and develop a high-performing verification team. Technical Background ASIC/SoC Digital Verification. Strong SystemVerilog and UVM. Functional Verification and Coverage Closure. Formal Verification. RISC-V processor and SoC verification. Experience leading verification projects or mentoring DV engineers. Why Consider ...

A leading semiconductor technology firm is seeking a Staff GPU Hardware Design Engineer to utilize silicon design skills in creating advanced solutions. The successful candidate will collaborate with cross-functional teams to design, debug, and ...